Hardening a Real-Time Operating System for a Dependable RISC-V System-on-Chip

In safety-critical systems, solutions that rely on redundancies at the hardware and software levels allow these systems to operate in radiation-harsh environments. In the literature, software-based techniques for enhancing reliability in critical systems are less developed when compared to hardware-based fault-tolerant techniques. In this context, we implemented error correction and detection techniques through software, along with a custom RISC-V processor-core implementation. RISC-V is an open instruction set architecture that is gaining popularity due to its modular design, as well as the FreeRTOS kernel, which is a well-established Real-Time Operating System. Our implemented proposal has shown to be able to reduce the number of execution failures by four times when compared to the standard version at the cost of increased execution time and energy consumption. The experimental results may guide designers in choosing the best trade-offs between reliability and resource constraints in complex contexts such as space applications.