EnSAFe: Enabling Sustainable SoC Security Auditing using eFPGA-based Accelerators

The utilization of reconfigurable and flexible acceleration for compute-intensive kernels, e.g., neural networks, crypto-engines, and arithmetics, have been on the rise in recent years, where embedded FPGA (eFPGA) architecture, as a de facto solution, is becoming an integral component of the system-on-chip (SoC) for the acceleration purposes. In the meantime, modern SoCs are getting larger and more complex in size and functionality, and with the inclusion of more IPs along with the eFPGA accelerator, they are getting more exposed to a wide variety of security-critical and sensitive information, hence innovative security infrastructure is needed to ensure the information security, i.e., integrity, confidentiality, and availability. Also, in an SoC equipped with the eFPGA-based accelerator, with the potential reconfigurability over time, sustainable and upgradable security infrastructure becomes a necessity. To address such concerns, in this paper, we introduce EnSAFe, a framework for enabling security policy auditing with upgradability within the designs enabled by eFPGA-based accelerators. The EnSAFe framework enables signal monitoring in a plug-and-play fashion, and the monitoring core logic will be mapped onto the eFPGA accelerator component with minimal overhead (almost zero). Our experiments demonstrate that the EnSAFe framework can detect runtime threats/vulnerabilities with a low area overhead.