Automatic Generation of Repair Suggestions for Control Logic of I&C Systems

We present an approach for suggesting possible repairs for the control logic of I&C systems implemented in the form of function block diagrams (FBDs) during the design phase. Each FBD has a set of functional requirements formulated using linear temporal logic (LTL). To ensure the correctness of the implementation, an FBD is translated into SMV, the language of the NuSMV model checker, which verifies the model against its properties. If a property does not hold, NuSMV generates a counterexample. In previous works, we developed methods on visual counterexample explanation using both, the failing LTL formula and the FBD itself. The current work continues in this direction and utilizes the results of the counterexample explanation to suggest fixes to the FBD considering the failed properties and the whole set of requirements. We propose three strategies for fixes generation and experiment on the examples of the logic from the nuclear domain.