New design optimization methodologies of aeronautic boards embedding SERDES up to 40 Gbps: tradeoff between performance and cost

The evolution of printed circuit technologies over the years has enabled them to acquire better density and finer engraving. Data rates and clock speeds increase with reduced switching times and power consumption over ever-smaller spaces.To ensure that these evolutions do not affect signal integrity, high-speed signal quality simulations and measurements are required. Simulation can predict potential weaknesses before manufacturing, while measurements help identify design failures and build confidence in simulation results for future board designs.Analyzing and optimizing every potential discontinuity has become an essential part of signal integrity. Factors that affect signal quality include signal attenuation, impedance matching, crosstalk, and jitter. Signal attenuation occurs due to dielectric and conductive losses. Signal integrity (SI) analysis should no longer consider the dielectric as homogeneous and the copper as a flat surface. It must take into account its actual structure within the PCB and its anisotropic and frequency-dependent properties.These effects will be studied for serial high-speed links (Serdes with PCIe and Ethernet) up to 40Gpbs.