A Wideband Bi-Directional 6-bit Passive Vector-Sum Phase Shifter Optimized Using Greedy Algorithm in 65-nm CMOS

A wideband 6-bit bi-directional passive vector-sum phase shifter (PVSPS) implemented in 65-nm CMOS technology is presented. The design employs two high-bit attenuators as gain tuning modulators, which consume no power and can achieve high-resolution gain attenuation with a 12-bit control code. A differential 90° coupler, serving as a quadrature network, generates the orthogonal vectors. The transformer-based input and inter-stage matching network are designed to obtain a wideband impedance matching performance. A code selection method based on the greedy algorithm is applied to choose proper operation states. The proposed PVSPS with 360° phase-shifting range exhibits accurate phase shifting (i.e., RMS phase error 0.56~1.92°/ 0.22~0.39°) and low gain error (i.e., RMS gain error 0.49~0.60 dB /<0.37~0.47 dB) in bi-directional operation.