MMSE Equalizer Design Optimization for Wireline SerDes Applications

This paper presents analytical equations for optimizing feedforward equalizer (FFE) and decision feedback equalizer (DFE) parameters in a wireline receiver to speed up system-level design and simulations. A minimum mean square error (MMSE)-based approach is applied to the receiver model, and a set of equations is developed to co-optimize FFE and DFE taps. The equations consider the noise sources in wireline links, including the sampling clock jitter. It also considers the effect of the noise correlations on the equalizer parameters. For sampling clock jitter, two separate models are developed to distinguish between sampling for discrete-time and continuous-time FFEs (pre-and post-FFE sampling). Then, the translation of jitter noise to voltage noise is carefully investigated. Jitter noise can be either white or correlated. Later, the developed model is modified to generate different variants of MMSE-based approaches to be used in various practical scenarios a designer may face. This includes the equalizer design for maximum likelihood sequence estimation (MLSE)-based receivers and equalizer design with bounded DFE tap magnitude to control undesired side effects such as error propagation. Finally, the use of “tap skipping” to save FFE hardware resources is investigated. The accuracy of models and the performance of each method is justified through simulations and comparing against the LMS adaptation loops.