Synthesis of Register Files for Low-Power Heterogeneous Digital Systems Based on FPGA

Field Programmable Gated Array (FPGAs) devices are widely used today. Due to their high integration, FPGAs are used in complex, energy-efficient digital projects. An important component in these systems is register files (RF). Because RFs are highly used in these systems, they contribute a significant factor in energy consumption. In this article we present two asynchronous RF architectures aimed at reducing power consumption. Both architectures are implemented in FPGAs in the traditional way, i.e. they are based on LUTs (Look-Up-Table) and Flip-Flops. When compared to synchronous RF, the proposed asynchronous RF achieved a power reduction of up to 38.8%.