Design of Locally-Clocked Asynchronous Finite State Machines with no Memory Elements

Synchronous Finite State Machine (FSM) controllers are extensively employed in the design of control units for complex digital systems. These systems can be realized on Field Programmable Gate Arrays (FPGAs), but they often face challenges associated with the global clock signal, such as clock skew and increased power consumption. In this context, the asynchronous paradigm offers intriguing characteristics that can serve as an alternative for design. However, Asynchronous FSMs implemented on the FPGA platform are highly susceptible to essential hazards arising from significant delays between logical blocks. One effective solution to mitigate hazards is the insertion of delay elements into the feedback of Asynchronous FSMs, which can be a challenging task on the FPGA platform. This article presents a novel architecture and approach for the synthesis of locally-clock Asynchronous FSMs that are free from essential hazards. The proposed locally-clock Asynchronous FSMs are described using the Extended BurstMode (XBM) specification. Unlike existing local clock architectures in the literature that employ latches or flip-flops to store states, our architecture is based on Huffman’s architecture, utilizing feedback combinational functions. Through a comparative analysis with existing locally-clock Asynchronous FSMs in the literature, our approach demonstrates the potential for achieving superior cycle time and latency performance.