Synthesis of QDI Combinational Circuits Based at the New Factorized DIMS

Clock signal-related issues in contemporary synchronous circuit designs have prompted the exploration of asynchronous circuits as an alternative solution. Asynchronous circuits operate based on events, eliminating the need for a clock signal. Among the various classes of asynchronous circuits, quasi delay insensitive (QDI) circuits offer simplified timing analysis and exhibit robustness against variations in process, supply voltage, and temperature (PVT). However, QDI circuits often suffer from high area overhead due to the utilization of delay-insensitive coding and an excessive number of C elements. In this paper, we propose a new method for optimizing QDI combinatorial circuits, referred to as QDI-CC. This method leverages factored equations to achieve the desired optimization. The QDI-CC circuits are implemented using basic gates and C elements, and they interact with the environment through strong indication, ensuring a high level of robustness in their environmental interactions. To evaluate the effectiveness of our proposed method, we conducted experiments on a set of eight benchmarks and compared the results with three existing methods from the literature. The analysis demonstrates that our proposal achieves significant improvements, with an average reduction of up to 35.5% in the number of transistors required.