DrPCE-Net: Differential Residual PCE Network for Characteristic Prediction of Transistors

Data-driven machine learning (ML) has emer- ged as an effective approach to providing insights into transistor devices prior to manufacture. Despite its success, most ML methods rely on deep learning to provide powerful fitting capacity. Consequently, they are generally data-demanding and computationally intensive, making them less attractive in practice. To resolve this challenge, we propose differential residual polynomial chaos expansion network (DrPCE-Net), a hybrid model framework that significantly improves traditional deep learning networks and delivers a consistent and accurate characteristic prediction for transistor devices. Specifically, the superiority of DrPCE-Net is achieved by the combination of: 1) a skip connection based on classic statistical regression, namely, polynomial chaos expansion (PCE) to provide a rough yet efficient estimation and 2) a deep learning network that fine-tunes the model to subtle variations and provides a smooth and accurate current response curve by utilizing high-order derivatives (HODs) information. DrPCE-Net is extensively assessed on gate-all-around (GAA) in various cross sections, which highlights its superiority over the state-of-the-art methods with a large margin—with up to 60% improvement in predictive accuracy over the state-of-the-art deep learning models.