Systolic Array Architecture for Educational Use

This paper presents a systolic array architecture for General Matrix Multiplication. The system was designed and verified using the Verilog description language. The architecture was constructed for educational use aiming to complement the practical activities of Computer Architecture classes. The proposed solution can be used as a design space exploration tool for evaluation of matrix multiplication accelerators based on non-stationary systolic arrays. Both the width and format of the processed operands as well as the number of stages of the systolic array’s Processing Elements can be customized. As a case study, the design and performance of a systolic array for accelerating the multiplication of square matrices of signed, 8-bit integers, is presented. The overall architecture was synthesized for the Altera DE2 FPGA board in order to evaluate its performance.