Selective High-Latency Arithmetic Instruction Reuse in Multicore Processors

In this work, we present an original contribution which augments the Intel Nehalem multicore architecture with a selective high-latency arithmetic set-associative reuse buffer. The architecture is simulated using Sniper, which we adapted to estimate the power consumption, area of integration and chip temperature, including latency modifications for the newly added unit. The implementation of a set-associative reuse buffer is a new approach, along with the applicability in a multicore microprocessor, applied to long-latency arithmetical instructions targeting dataflow bottleneck and increasing CPU performance. Additionally, we have performed a manual design space exploration for the enhanced microarchitecture, by varying the associativity and the size of the proposed reuse buffer unit and evaluating the impact on the interested metrics. Our simulations on the Splash 2 benchmarks, revealed an average reuse rate up to 33.27% allowing a maximum speedup of 6.56%. While the energy consumption remains stable, we see an average chip temperature reduction of 2.8°C along with the increase in associativity.