Verilog Implementation and Functional Verification of Hybrid Cryptography Algorithm

On today’s platforms, on-chip network communication has become important significance. The security of data has become more significant during the transmission of data between the peripherals. There might be a need of some encryption standards to prevent corruption of data. Data Encryption Standard(DES) and Advanced Encryption Standard(AES) are symmetric encryption and decryption algorithms.This work mainly focuses on understanding the working of both the algorithms and to design a hybrid cryptography algorithm by combining the features in both AES and DES algorithms. Dual Coupled Linear Congruential Generator(DCLCG) has been used for key generation process. After performing all the stages of encryption like key generation, substitution, permutation, key expansion, encryption rounds the cipher text is available. The secret key and the encrypted text is given as input for decryption and all the other process are done in reverse order. After the designing is completed, the design is functionally verified using the System Verilog in QuestaSim and achieved the coverage of 83.33%. Then certain parameters like timing, complexity, efficiency and area requirement has been calculated using the Vivado design suite and avalanche effect algorithm. It was found that proposed algorithm takes only 12 ns for encryption but conventional algorithm takes 18 ns. Then the area requirement is 116 LUTs, which has been increased because the keyed permutation takes more area as it has more number of S-Box permutation stages.