A Low-Power Charge-Domain Bit-Scalable Readout System for Fully-Parallel Computing-in-Memory Accelerators

Computing-in-memory (CIM) accelerators have the characteristics of storage and computing integration, which is becoming an important solution for optimizing the computational performance of large-scale neural networks. The readout system plays a crucial role in the CIM accelerators, with power consumption accounting for a significant proportion and speed determining the overall bandwidth. In this paper, a low-power charge-domain bit-scalable readout system design is proposed for fully-parallel CIM accelerator. The charge-domain accumulator supports bit-scalable calculation modes of 2-bit, 4-bit and 8-bit for weight data by capacitor array configuration, which avoids using digital accumulators with large bitwdith. Additionally, the use of charge-domain post-weighting method for input data helps reduce power consumption with less analog-to-digital conversion. Experimental results demonstrate that the integral non-linearity (INL) and differential non-linearity (DNL) of the accumulator output voltage VOUT of in each mode do not exceed 1 LSB, ensuring excellent linearity and accurate bit-scalable MAC calculations. Moreover, the proposed charge-domain CIM accelerator with ReRAM macro cells achieves an average energy efficiency of 180.61 TOPS/W and a normalized peak energy efficiency of 1618.0 TOPS/W on mixed-precision ResNet-18 networks.