Measurement of wall voltage in reset discharge of AC plasma display

Summary form only given. In AC plasma display, it is very important to quantify the wall voltage induced by the wall charge accumulated on the dielectric surface. If we know the quantities of the wall voltage in each period of every sequence; reset period, address period and sustain period, then it helps us to design the optimal driving waveform for high efficiency plasma display.. The purpose of this study is to experimentally measure the exact wall voltage profiles at each period of every sequence and then provide the basic data to driving sequence designer. In this study, we develop a new method to measure the wall voltage with VDS (Versatile Driving Simulator) system and it is more simple and better method than charge-voltage (Q-V) Lissajous analysis method. And then the wall voltage has been experimentally measured at the reset period by this new method. The reset period in driving sequence of plasma display plays an important role in improvement of the display quality. All unit cells in panel is initialized and is settled to have same amount of wall charge in reset period of driving sequence, and stable initialization of wall charge state for all unit cells can improve the accuracy of write discharge in address period. It is very important to know the wall voltage quantity and wall charge state for design of the optimal reset driving waveform, which enables perfect initialization. Toward this end, the wall voltage quantities and wall charge states in reset period have been experimentally measured for various reset conditions by use of new method in this experiment. The ramped detecting pulse method, which is newly introduced method to measure the wall voltage quantity and the wall charge state, has been developed. We could simply measure the wall voltage by just inserting a ramped detecting pulse at the observance timing position and making observations of the breakdown voltage on rising or falling slope of ramped detecting pulse. The wall voltage quantities and wall charge states in reset period have been experimentally measured for various reset conditions by use of this new method. In square reset, the applied reset voltage must be over 330V and the reset pulse width must be longer than -5us for perfect initialization and stable writing address. When the reset pulse width is shorter than -5/spl mu/s, the polarity of wall charge is changed by strong self erasing discharge. It is noted that the wall charge increases as the rise time of reset pulse increases and the rise time of reset pulse must be shorter than -1/spl mu/s for perfect initialization and stable writing address. It is also noted that the wall charge increases as the fall time of reset pulse increases and the fall time of reset pulse must be shorter than -1/spl mu/s for perfect initialization and stable writing address. The space charges decay within 100/spl mu/s and it depends on the reset voltage, because the reset voltage determines the existence of self erase discharge in this experiment.