Si Interlayers Trimming Strategy in Gate-All-Around Device Architecture for Si and SiGe Dual-Channel CMOS Integration

A practicable Si interlayers trimming strategy to attain thinned nanosheet (NS) using an in situ steam generation (ISSG) oxidation and removal process has been proposed for Si and SiGe dual-channel CMOS integration. After adopting the Si interlayers trimming strategy, four-level Si NSs were uniformly thinned from ~11.0 to ~6.4 nm and its device features excellent electrical performance, such as SS = 65 mV/dec, DIBL = 11 mV/V, and
${I} _{\text {on}}/{I} _{\text {off}}$
=
$4.7\times 10^{{5}}$
. This can be attributed to the fact that better gate control and electrostatic capability is achieved due to NSs thinning. Meanwhile, as gate length further scaling, Si interlayers trimming strategy exhibits better short-channel effect (SCE), which is verified by technology computer-aided design (TCAD) simulation. Additionally, the effect of Si interlayers trimming on the threshold voltage (
${V} _{\text {TH}}$
) is comprehensively investigated. It is confirmed that the decrease in
${V} _{\text {TH}}$
is caused by the changes in metal gate-stack filling between NSs, changes in NS geometry, and geometry-dependent quantum mechanical (QM) effects.