Influence of the source/drain doping region on the reconfigurability of BESOI MOSFET

This paper studies experimentally the influence of the N+ doped source/drain regions on the back enhanced with separate contacts SOI MOSFET (
^BE
SOI SC MOSFET) reconfigurability. The reconfigurable FET (RFET) proposed in this paper resulted in a drain current level in the same order of magnitude for both types of configurations (nMOS and pMOS). These results present a significant balanced drain current compared with the others
^BE
SOI device fabrications versions. In
^BE
SOI SC MOSFET, with programming gate voltage of |V
GB
|=30V and drain voltage |V
D
|=0.1V, the
^BE
SOI drain current reaches a value of, approximately, −1.4 μA and 1.6 μA, working as pMOS and nMOS respectively, which can be considered very well balanced.