An Adaptive Word-Length Selection Method to Optimize Hardware Resources for FPGA-Based Real-Time Simulation of Power Converters

Power converters have become increasingly important in the power industry. To enhance design reliability and efficiency, real-time simulation is a popular method for testing control units of these devices. FPGA-based real-time simulation is considered a genuine alternative to CPU-based applications as control unit frequencies increase. Although automated tools can map simulation methods from floating-point high-level languages to fixed-point FPGA, manually selecting the fixed-point word length to meet precision requirements involves a significant amount of tedious and repetitive work. Word length selection also impacts FPGA hardware resource usage. This paper proposes an adaptive word length selection method under accuracy constraints to minimize hardware resources. The innovation lies in using error noise models to compute analytical expressions relating simulation model accuracy to word length. The adaptive word length selection process is combined with commercial high-level synthesis tools to achieve high resource optimization performance. A three-phase inverter example demonstrates the benefits of our method in calculating model accuracy and optimizing FPGA hardware resources in simulations.