Design of a High-Efficiency Low-Ripple Buck Converter for Low-Power System-On-Chips

This paper presents the design of a buck converter for use in low-power system-on-chips (SoCs) with a ripple voltage small enough to directly power sensitive analog circuits without the help of low-dropout voltage regulators (LDOs). To minimize the ripple voltage while maximizing the converter’s light-load efficiency, we employ a pulse-frequency modulation (PFM) scheme and a fast duty-cycled comparator to control the converter’s output voltage. The duty cycling of the comparator, automatically performed by the Sleep State Controller (SSC), helps improve the light-load efficiency by 48%. Fabricated in a 0.18-
$\mu \text{m}$
CMOS process with an active area of
$0.42 ~\mathrm {mm}^{2}$
, the proposed low-ripple buck converter achieves the ripple voltage of
$1.6~ \mathrm {mV_{pp}}$
and the overall efficiency of higher than 74.4% over the load current range from
$1.2 \mu \text{A}$
to 1.8 mA.