Experimental Evaluation of Jitter Reduction Methods for Multi-Gigahertz Test

This paper describes three methods for reducing random jitter (RJ) in Multi-GHz electronic test instruments. These are based on real-time averaging of periodic signals (clocks or reference signals). In each method, N multiple signals are phase-aligned and averaged to reduce jitter by (1/N)
^1/2
. The first method uses multiple phase-locked sources and is evaluated at 1 GHz and 10 GHz. The second method uses integer-cycle delayed copies of a single source and has been shown effective at 4 GHz. A novel third method is introduced and characterized up to 10 GHz using multiple tuned delay line stubs. The three methods can be used individually or in various combinations as well as with traditional techniques (e.g., PLL-based methods). In one example, RJ~300 fs jitter is achieved using a single stage that combines two of the methods, starting with input RJ
Source
~700 fs. Simulation of multiple-stage configurations suggest that “ultra-low” (100–200 fs) jitter may be feasible.