Structured DFT Development Approach for Chisel-Based High Performance RISC-V Processors

Research has shown that agile language Chisel and related agile design methodology is promising to sustain the scaling computing performance in a more efficient way. Design For Test, as an economical and effective method for chip production testing, must be integrated into the agile development system to meet the requirements of mass production. Due to the lack of support for the traditional EDA toolchain, chip development through Chisel has not been widely accepted in the industry. This paper is based on the research of XiangShan, an open-source project for RISC-V high-performance processor. XiangShan establishes a structured DFT(degisn for test) development approach and Chisel-based DFT agile design flow. XiangShan develops a flexible chisel-based XS-shared bus mbist interface to improve design PPA and proposes the MarchSLD algorithm to enhance defect detection in the FinFet process node. XiangShan’s DFT development Approach is moving towards hierarchical, flexible, and reliable in two generations of processors. Experimental results show that the optimized Chisel-based DFT design flow can support agile development requirements and achieve industry-competitive performance.