Parametric Faults in Computing-in-Memory Applications of a 4kb Read-Decoupled 8T SRAM Array in 40nm CMOS

Computing-in-memory (CIM) circuits can energy-efficiently conduct the massive multiply-and-accumulate (MAC) computations required by artificial neural networks (ANNs). However, the CIM’s resolution relies on a fundamental assumption of the CIM design: all memory cells output the same current to their read bitlines (RBLs) given the same read wordline voltage and stored weight bit. In practice, parametric faults due to the devices’ intrinsic process variations may introduce significant errors to the MAC results. This work implements accurate test circuits with a 4kb read-decoupled 8T (RD8T) SRAM macro in 40nm CMOS to investigate the parametric faults caused by the intrinsic process variations. Our measurement results reveal the detailed spatial distribution of the RD8T cells’ output currents and suggest that the CIM accuracy can be improved by calibrating the gain errors of the RBLs.