The Efficiency of High-performance SHA-3 Accelerator on the System Level

The Secure Hash Algorithm-3 (SHA-3) has become increasingly vital in numerous security applications within the Internet of Things (IoT) field. Given the diverse purposes, SHA-3 serves in the IoT landscape, the need for versatility is essential. Additionally, recent studies have primarily focused on achieving high performance and optimizing resource utilization for SHA-3. However, these studies have overlooked the crucial aspect of data transfer between the external memory and the hash function block, as transfer time plays a significant role. This paper proposes an efficient SHA-3 architecture designed for System-on-Chip (SoC) based on a Field Programmable Gate Array (FPGA) called system-level SHA-3 accelerator (SSA) to address the aforementioned challenges and be suitable for real edge computing. The SSA contains three key proposals. Firstly, the proposed padding architecture is designed from a combination of Serial Input to Parallel Output (SIPO) and a barrel shifter, which is well-suitable for managing the data transfer process on the system. Secondly, implementing a two-stage pipelining within the Round Function (RF) to reduce critical path delays and make a high occupancy. Finally, designing four modes (SHA3-224, SHA3-256, SHA3-384, and SHA3-512) enables the SSA to compute various SHA-3 to support a wide range of applications. Our architecture is implemented on the DE10-Standard Development Kit (Cyclone V SX SoC-5CSXFC6D6F31C6N), which is integrated into the FPGA and is controlled by a Dual-Core ARM Cortex-A9 processor. The result is up to 38.34 Gbps in throughput and 5.61 Mbps/ALM in efficiency for the RF computation, 28.02 Gbps in throughput, and 3.63 Mbps/ALM for the full proposed architecture.