FPGA Accelerator for Human Activity Recognition Based on Radar

Radar-based human activity recognition (HAR) has great potential in many applications. The deployment of HAR in many practical applications requires the system to be energy-resource efficient. In this brief, we propose a lightweight dedicated hardware accelerator for radar-based HAR. In particular, the specific property of radar signals are taken advantages of to optimize the 1-D convolutional neural network (CNN) model for HAR. Based on that, a dedicated hardware architecture is further proposed to exploit the advantages of the optimized CNN model. We build a prototype system on field programmable gate array (FPGA) to validate and demonstrate the proposed design. We also map the proposed accelerator to 55 nm CMOS technology. Experimental results show that the performance as well as the energy-resource efficiency of the proposed design are significantly higher than other existing vision-based HAR systems.