Aging Protected Two Stage CTLE For High Speed Data Recievers

The proposed architecture protects two stage CTLE from aging phenomena. The solution implements additional devices to set different nodes of the circuit to different intermediate voltage levels and prevent them from high stress operating conditions. The added circuitry is estimated to cost 13% increase of the CTLE layout. Aging simulation results show that after 10-year operation the performance degradation is reduced from 45% to less than 5% due to the added protection system.