In-Memory Fault-Free Vector Simulation

A technology for modeling and in-memory simulation of digital devices based on smart data structures is proposed. The fault-free method for modeling and simulation of digital devices based on vector logic, located in memory based on read-write transactions, is considered. In-memory fault-free simulation on smart data structure is focused on implementation in-memory of SoC, FPGA, RISC-V VLSI. The proposed method of in-memory simulation of logic circuits does not require synthesis and implementation in the standard base of elements. Moreover, the performance of the method depends on the size of the elements, the more inputs, the higher the parallelism of processing the input test sets as addresses. Based on good behavior simulation, a system for stuck-at-fault simulation of logical functionality, as well as logical circuits, is built. The software application is focused on teaching university students the methods of verification and testing of digital products. A convenient visual interface of the application can serve student projects that include dozens of logical elements of any complexity.