A Power Supply Rejection Based Approach for Robust Defect Detection in Operational Amplifiers

This manuscript presents a comprehensive all-digital design for testability (DfT) approach which achieves high coverage in detecting defects in operational amplifiers (op amps) along with their reference and bias circuits. The proposed method has the capability of been applied both at production test and for on-line health monitoring post-deployment to detect zero-time and latent defects. The built-in self-test (BIST) circuitry is simple to design, occupies negligible area and exerts minimal to no influence on the op amp's regular performance. The proposed method is based primarily on DC parametric sweep which significantly shortens the test time and consequently leads to a substantial reduction in production test costs. Additionally, due to the digital nature of the method, it can also easily be implemented with existing digital testing infrastructure like IJTAG on a system on chip (SOC). Furthermore, in this work we introduce the duo digital window comparator, a novel detector for testing defects in the Widlar reference and the bias circuitry. We validate our method using extensive transistor-level simulation of a two-stage miller compensated folded cascode amplifier along with widlar reference and current bias circuit. Simulation results show that proposed method achieves a high defect coverage of 99% in main amplifier and 100% in widlar reference and bias circuitry. All the designs in this work are implemented in TSMC 180nm technology.