Physical Design of 6T Cell of SRAM Devices and Comparative Analysis of Layout

The article discusses the possibilities of physical design of the most common 6T memory cell of modern SRAM devices and the physical design of 16-bit and 256-bit memory array based on it with 5 nm technology node. In the work, based on the schematic solution of the memory cell and information about the base of the used transistors and interconnections, five layout solutions of the 6T memory were proposed using two layers of metal. Based on them, the topology of array with 16, and 256 bits of memory were developed. Physical and schematic engineering simulations were performed for the proposed topological solutions. Based on the obtained results, a comparative analysis of the proposed layout solutions were performed in terms of the occupied area, current consumption and read/write delay times, temperature, supply voltages and process variation over a wide range.