Graph Theory Based Defect Simulation Framework for Analog and Mixed Signal (AMS) Circuits with Improved Time-Efficiency

In AMS circuits, the defect simulation time is increasing prohibitively as the circuits are becoming more and more complex. In addition to this, as the need for high defect coverage is increasing due to standards such as ISO26262, the defect simulation time is further increasing. In this paper, we present an ultra-fast defect simulation framework to test defects in pre-silicon testing of AMS circuits. We achieve time efficiency by means of two methods: (1) Improving the defect injection mechanism and (2) Circuit partition. To realize a given defect model, we use Verilog-A modules using which we can inject nearly all the defects in a circuit with a single test run (for a given test condition) which reduces the average defect simulation time. In addition to this, we also incorporate partitioning of the circuit under test into sub circuits using graph theory. The main idea here is that testing individual strongly connected components (SCCs) separately is comparatively more time-efficient rather than testing the entire circuit together. For robust framework validation, we utilize a benchmark circuit containing common analog circuits like operational amplifiers, bandgap references, Widlar current references, and bias generation circuits designed in UMC65nm technology. For the defect detection, we consider the voltage values at strategically chosen voltage nodes in the circuit and compare them with the values expected from a defect-free circuit. Using extensive simulations, we show that using our method, the defect simulation time can be improved by 17X in comparison with conventional methods. Additionally, the proposed method is independent of defect model or detection method.