In-Memory Fault as Address Simulation

A technology for modeling and in-memory simulation of digital devices based on smart data structures is proposed. A method for modeling and simulation faults as addresses is proposed for analyzing the quality of logic circuit tests based on the use of truth tables and deductive vectors. Simple formulas are proposed, which have no analogues, for fault modeling and simulation, for the synthesis of deductive matrices, and for the fault-free simulation of logic elements. Smart data structures and algorithm based on read-write transactions are being developed for in-memory fault-free simulation of digital functionality. Smart digital-logic structures (GL, RTL, SL) are implemented in any memory without complex and expensive synthesis procedures. Vector-tabular in-memory simulation of single and multiple stuck-at faults (as addresses) of functional elements of an arbitrary number of inputs is proposed. Truth table is proposed to describe the tested combinations of input lines faults. Instead of a processor, read-write transactions are used on smart data structures. A vector-logical synthesis of deductive matrices for fault simulation is proposed, which has a quadratic computational complexity. Input data for synthesis: input test set and logical vector of functionality. The essence of simulation is the superposition of three components: the input test vector, its derivative: the fault truth table and the deductive matrix obtained from the logical vector. The superposition of explicit structures of single-format smart data means that there is no simulation algorithm for obtaining a list of faults to be detected on the test. An automaton for deductive fault simulation (as addresses) of logical elements of the digital circuit is also synthesized. In-memory fault simulation on smart data structure is focused on implementation in SoC, FPGA, RISC-V, VLSI.