Modeling Faults as Addresses

A smart data architecture is proposed for simulating faults in digital circuits, as in-memory computing. The purpose of such computing is to reduce energy consumption and latency when simulation of logic circuits by replacing processor instructions fast read-write transactions on logic vectors in memory. To do this, it is proposed to leverage vector form of the truth table, which are used to construct deductive matrices of logical elements. The axiom is used: the truth table of tests T, the logical functionality of the element L and faults F are identical in form to each other and always convolutely interact with each other
$\mathrm{T}\oplus \mathrm{L}\oplus\mathrm{F}=0$
. The deductive matrix is seen as the genome of logic to solve all design and test problems. To do this, based on the logical vector, smart data structures are built that can minimize the complexity of the fault simulation and the good operation algorithm of the digital product. Deductive mechanisms for modeling faults, like addresses, are proposed based on read-write transactions on smart and explicit data structures in the form of vectors, tables, and matrices. A superposition of smart and explicit data structures based on logical vectors and truth tables is proposed, which already forms a solution. Therefore, such data does not require simulation algorithms, but requires modeling algorithms, for good superposition of explicit data structures, which leads to a solution without simulation. A software architecture is proposed for solving problems of fault modeling, good behavior and test generation based on smart data structures. The results of processing same digital fragments for the verification of data structures and modeling and simulating mechanisms implemented in the python code are presented.