Dynamic delta sigma ADC with variable clock on 65 nm CMOS

The dynamic delta-sigma ADC presented in this paper is based on a continuous-time delta-sigma modulator (CT-DSM), a two-stage digital filter, and a digital control circuit for switching the clock frequency. The CT-DSM was implemented on a test chip in 65 nm CMOS technology at a supply voltage of 1.2 V, and the digital part of the ADC was implemented on the FPGA, which includes the two FIR filters and the controlling unit/block for clock frequency. In the presentation of the measurement results, special focus is placed on the effects and performance of frequency switching in the analog part of the CT-DSM.