A fully differential 3-stage CMOS op-amp for high-speed sampling applications

In this paper, we present a fully differential 3-stage amplifier suitable for high-speed applications. The proposed opamp uses a resistor-loaded topology to achieve high bandwidth and the 3-stage offers the desired dc gain. A nested miller technique is used for the frequency compensation for the op-amp. The 3-stage fully differential op-amp is designed in TSMC 65 nm technology with a power supply of 1.2 V. The schematic simulations exhibit a DC gain of 53 dB, the unity gain- bandwidth & phase margin are 750 MHz & 70° respectively, and a total power consumption of 1.6 mW.