Timing Analysis of Embedded Software Updates

We present ReTA (Relative Timing Analysis), a differential timing analysis technique to verify the impact of an update on the execution time of embedded software. Timing analysis is computationally expensive and labor intensive. Software updates render repeating the analysis from scratch a waste of resources and time, because their impact is inherently confined. To determine this boundary, in ReTA we apply a slicing procedure that identifies all relevant code segments and a statement categorization that determines how to analyze each such line of code. We adapt a subset of ReTA for integration into aiT, an industrial timing analysis tool, and also develop a complete implementation in a tool called Delta. Based on staple benchmarks and realistic code updates from official repositories, we test the accuracy by analyzing the worst-case execution time (WCET) before and after an update, comparing the measures with the use of the unmodified aiT as well as real executions on embedded hardware. Delta returns WCET information that ranges from exactly the WCET of real hardware to 148% of the new version's measured WCET. With the same benchmarks, the unmodified aiT estimates are 112% and 149% of the actual executions; therefore, even when Delta is pessimistic, an industry-strength tool such as aiT cannot do better. Crucially, we also show that ReTA decreases aiT's analysis time by 45% and its memory consumption by 8.9%, whereas removing ReTA from Delta, effectively rendering it a regular timing analysis tool, increases its analysis time by 27%.