Performance Estimation and Prototyping of Reconfigurable Near-Memory Computing Systems

The concept of near-memory computing (NMC) has emerged as a promising solution to address the memory wall challenges faced by future computing architectures. By utilizing modern systems that integrate 3D-stacked DRAM memory, the NMC paradigm minimizes unnecessary data movement between the memory subsystem and the CPU. FPGA vendors have incorporated 3D-stacked memories into their products to meet the increasing bandwidth requirements of memory-intensive applications, enabling FPGAs to compete with GPU solutions in terms of speed and energy efficiency. Recent NMC proposals focus on different data processing workloads, including graph processing and machine learning. This work addresses the research questions of how to leverage the full bandwidth of 3D-stacked high-bandwidth memory and how to facilitate the adoption of the near-memory computing paradigm.