A Novel Design of FPGA-TDC Based on SerDes

Time interval measurements are widely used in automatic test fields such as time-of-flight measurements, spectral analysis, and circuit troubleshooting. With the blowout development of integrated circuits, the measurement of signal timing parameters such as digital signal delay and setup/hold time has put higher and higher demands on the performance of time-to-digital converters (TDC), such as measurement speed and configuration flexibility. In FPGA-based TDC design, the delay chain is usually formed by cascading standard gate circuits. In contrast, such TDC calibration could be more convenient due to the gate delay's poor consistency and significant temperature drift. Besides, its unipolar triggering feature cannot meet the digital signal edge polarity identification demand. To address these issues, a novel design of TDC based on Serializer/Deserializer(SerDes) is proposed in this paper. In our design, we utilize SerDes to digitally sample the signal after shaping at high speed and deserialize the data. Then the parallel data are computed and processed in real-time in FPGA. The design binds the uniformity of the delay unit to the period stability of the sampling clock, which significantly improves the nonlinear performance of the TDC and avoids complicated calibration. Also, the high-speed sampling with a reconfigurable clock makes it flexible for various types of circuit measurement. The sampled data down-speeded by SerDes can be processed in real-time without interruption in the FPGA, thus achieving continuous time-to-digital conversion. Moreover, the two-level positioning of leading/trailing edges accurately identifies the position and polarity of signal edges and ensures high resolution while realizing a large measurement range. Extensive experiments prove the effectiveness of our design.