Parallel Acceleration Algorithm for Eye Diagram Construction Based on GPU

The time margin is decreasing dramatically with serial bus development, making signal integrity a crucial concern in high-speed digital systems. As an efficient means to assess signal integrity, eye diagrams are extensively used in electronic test instruments. Hang on the structure of test instruments, data acquisition and data processing are performed alternately. Occasional signals will be omitted during the processing episode of test instruments. Thus, the capture capability of the test instrument mostly depends on its data processing speed. However, conventional eye diagram construction methods based on serial processing consume much time, resulting in the insufficient capability of capturing occasional signals. To increase the capture capability, an eye diagram construction algorithm based on parallel processing is proposed in this article. The proposed algorithm can be implemented in Graphics Processing Unit (GPU) with a high processing speed, which remarkably accelerates eye diagram construction in electronic test instruments. In addition, it provides a color-graded display style, making it easier for engineers to detect signal integrity issues. Experimental results indicate that the speed of constructing an eye diagram by our algorithm is significantly faster than the serial algorithm implemented in Central Processing Unit (CPU). The proposed eye diagram construction algorithm has contributed to the field of electronic test and diagnosis. It plays a role in quickly diagnosing signal integrity issues in high-speed digital circuits.