Future directions in clocking multi-GHz systems

Summary form only given. This tutorial addresses the problems and possible solutions of clocking digital systems operating at multi-GHz frequencies. We address techniques for managing clock uncertainties and clock power in synchronous circuits. There are two trends that are disturbing: (a) the power taken by the clock distribution network and clocked storage elements (flip-flops and latches) is increasing relatively to the rest of the logic, (b) clock uncertainties are taking a significant portion of the cycle away from useful logic operations. We present ways of designing clock storage elements that are capable of absorbing a significant portion of clock uncertainties and passing delay from one logic stage to the other. At multi-GHz frequencies of operation it will be difficult to precisely control the timing boundaries between the logic stages. Thus the ability to extend the operation into the time period allocated for the next pipeline stage is important. This is known as time borrowing. Also, the ability to incorporate logic into the clocked storage elements is of critical importance given that the number of logic stages in a pipeline running at multi-GHz frequencies, is decreasing to less than ten.