HA/sup 2/TSD: hierarchical time slack distribution for ultra-low power CMOS VLSI

This paper describes an efficient hierarchical design and optimization approach for ultra-low power CMOS logic circuits. We introduce the Hierarchical Activity-Aware Time Slack Distribution (HA/sup 2/TSD) algorithm, which distributes the surplus time slack into the most power-hungry modules hierarchically. HA/sup 2/TSD ensures that the total slack budget is maximal and the total power is near-minimal. Based on these time slacks, we have optimized technology parameters (supply voltage, threshold voltage, and device width) through a gate-level power optimizer and have tested the algorithm on a set of benchmark example circuits and building blocks of a synthesizable ARM core. The experimental results show that our strategy delivers over an order of magnitude savings in total (static and dynamic) power and reduces the optimization run-time significantly.