Ultrathin high-/spl kappa/ gate dielectric technology for germanium MOS applications

For the first time, we have successfully demonstrated the use of a high-/spl kappa/ gate dielectric material, ZrO/sub 2/, for CMOS applications on a pure germanium substrate. Using a low-temperature formation technique, we achieved excellent C-V characteristics with hysteresis of 1.5 mV and a capacitance-based equivalent SiO/sub 2/ thickness (t/sub ox,eq/) of about 5 /spl Aring/. Additionally, excellent device uniformity and very high device yield were attained.