Closed-loop adaptive voltage scaling controller for standard-cell ASICs

The paper describes a closed-loop controller for adaptive voltage scaling (AVS) where the supply voltage to a standard-cell ASIC is dynamically adjusted to the minimum value required for the desired system speed. The controller includes a clock generator that provides a low-jitter clock to the ASIC at all steady-state operating points and through transients. To speed up the voltage transient response to step changes in clock frequency, the controller is based on a multiple-tap resettable delay line. A chip including the AVS controller and a dual 16-bit MAC application has been fabricated in a standard 0.5 /spl mu/ CMOS process. The area taken by the AVS controller is 0.12 mm/sup 2/. Experimental results demonstrate operation over the application clock frequency range from 80 kHz to 20 MHz, and a 38 /spl mu/s transient response for a step change in speed from standby to maximum throughput operation.