Research on SoC Architecture Model and its Application in BMS Scenario

According to the different application requirements in different scenarios, the design of system-on-chip hardware architecture is anisotropic, lacking a unified description of system-on-chip architecture components, as well as unified guidance and standards for design of each part. In this paper, a pentagon architecture model of system-on-chip design centered on kernel computing power, memory, peripheral interface, internal bus and power consumption is proposed. Based on this model, three typical architecture designs of system-on-chip are given by taking safety fault warning, charge and discharge control and battery state monitoring as examples, which provides qualitative theoretical guidance for architecture design of system-on-chip. This work has certain guiding significance for the demand-based system-on-chip architecture design in battery manage system scenarios.