Impact of Nanosheet Thickness on Performance and Reliability of Polycrystalline-Silicon Thin-Film Transistors With Double-Gate Operation

In this work, the polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) with double gates and nanosheet (NSH) channel structures were fabricated to investigate the impact of NSH channel thickness (t
_Si
) ranging from 15 nm to 2 nm on device performance and reliability. Thinning t
_Si
from 15 nm to 10 nm resulted in improved control of channel potential by the gate voltage, leading to a decreased threshold voltage (V
_TH
) and subthreshold swing (SS). However, further reduction of t
_Si
to 5 nm, while continuing to decrease SS, caused an increase in V
_TH
due to the grain size reduction and quantum confinement (QC) effects. Lastly, reducing t
_Si
to 2 nm resulted in an increase in both SS and V
_TH
mainly due to the QC effect. In terms of reliability, under a fixed positive gate bias stress condition, thinning t
_Si
enhanced the electric field stress, leading to more severe device damage. However, due to the enhanced ability of gate voltage control over the channel potential and the buried channel effect on electron transport resulting from thinning the channel thickness, there exists an optimal range between 10 nm and 5 nm for the selection of t
_Si
in terms of the degradation of V
_TH
, SS, and on-state current. Consequently, it is evident that for transistors utilizing NSH channels, the selection of t
_Si
is not a case of “the thinner, the better.” This finding highlights the need to consider the optimal t
_Si
range between 10 nm and 5 nm, balancing the performance and reliability aspects of the device design.