A 3.38-ppm/°C Voltage Reference for Harsh Environment Applications Empowered by the In-Loop Resistance Trimming Technique

This brief proposes a MOSFET-only voltage reference with a low temperature coefficient. By leveraging the resistances with positive and negative temperature coefficients in the loop, a voltage reference with a wide temperature range and low temperature coefficient is realized. Through the model analysis, we adjusted the resistance to provide appropriate offset for ZTC-MOS to achieve high-order compensation in a wide temperature range. Compared to the sole ZTC compensation, the proposed design achieves lower temperature coefficient. The chip was designed by the 0.18-
$\mu \text{m}$
BCD process and achieves a 3.38-ppm/°C temperature coefficient in −65°C to 225°C from post-layout simulation results, exploiting a novel methodology for power management integrated circuits design for niche high-temperature applications.