Parallel Optimization and Hardware Customization for Fast Fourier Transform

Fast Fourier Transform (FFT) is widely applied in many scientific and engineering applications. This paper aims to use parallel optimization and hardware customization techniques to improve the performance and energy efficiency of FFT. First, we illustrate two parallel FFT algorithms: intra-stage parallel algorithm (ISPA) and six-step parallel algorithm (SSPA). Then, we conduct a detailed performance analysis for the two parallel algorithms and find that SSPA has the better scalability. Lastly, we customize the FFT hardware core and integrate multiple cores in a system-on-chip (SoC) to accelerate the FFT workload. We compare the proposed multi-core FFT accelerator with mainstream FFT libraries including FFTW, Intel MKL and NVIDIA cuFFT. Experimental results show that our FFT hardware achieves higher energy efficiency.