Leveraging Approximate 4:2 Compressors for Improved Performance in an 8-Bit Dadda Multiplier Design

In recent years, the two primary design concerns in the digital world have been reliability and power consumption. In order to limit power usage new low-power architectural models were being introduced. The most basic components of computation are adders and multipliers, hence when constructing them low power consumption architecture must be considered. It is desirable to minimize the number of operations as this will lessen the dynamic power, which makes up a sizeable component of total power consumption. Approximate computation is one such ideal model for hardware implementation, and our approach proposes to build sixteen cases of approximate 8-bit Dadda multiplier to have a lower delay, area, and power dissipation. The application for image blending also uses the suggested multipliers.