Digit-Size Selection for FPGA Implementation of Generic Digit-Serial Multiplication Over GF(2m)

Multiplications over the Galois field GF
$(2^{m})$
are widely used for the realization of point operations in the elliptic curve cryptosystem (ECC). Implementation of these multipliers for resource-constrained applications possesses a significant research challenge. Efficient implementation of field multiplication is therefore an important area of research. We present here the design of generic digit-serial multipliers for GF
$(2^{m})$
and coded those using VHDL for different values of field order and different digit-sizes. We have synthesized the design using Xilinx ISE Design Suite version 14.4 and estimated the FPGA resource consumption such as the number of slice LUTs and slice registers, as well as, the minimum clock period required for different digit sizes for three different values of field order, such as
$m=64,193$
, and 239. Besides, we have estimated the minimum computational delay and slice-delay product for different digitsizes and different field orders in order to determine the digit size to be used for the minimum usage of LUT slices, the minimum delay, and the minimum slice-delay product. Interestingly, we find that for the digit-size,
$w=16$
the computational delay is the lowest for different field orders. It is observed that the number of slices and slice-delay product are minimum in the case of bitserial architectures for different values of the field order
$m$
.