RTL to GDSII Implementation of RADIX-4 Booth Multiplier using Opensource EDA tools

This paper aims to presents a fast, low power and optimum chip area architecture for Radix-4, 8-bit booth multiplier. Skywater 130nm CMOS technology node is used to achieve the desired Circuit synthesis and post-layout simulation. RTL to GDSII workflow is implemented by utilising open-source EDA tools from the Openlane framework. The proposed circuit implementation occupies an area of 16457.830 and consumes 494uW at 66.67 MHz. In comparison to existing 8-bit multiplier implementation, the proposed multiplier architecture is 33% faster and 11% lower power consumption. It also aims to demonstrate the capability of opensource EDA environment and the further advancement in opensource ASIC IP design.