Design and Implementation of High Reliability FIFO Based on FPGA

Developed a highly reliable FIFO for real-time Ethernet cards on trains utilizing the FPGA platform. An improved FIFO design scheme has been proposed to address the metastability issues that may arise in systems with multiple clock domains. After the second-level synchronization and gray code conversion operations across clock domains, a triple-mode redundant module is added to solve the data stability problem. Finally, the simulation verification was carried out through the Modelsim simulation platform. The simulation results show that in the case of abnormal data on one channel, the read and write function of the asynchronous FIFO are normal and the empty/full flag signals are correct, proving that the design meets the requirements for high reliability.