Analytical Volume Inversion Charge density Modeling of SGCG DG MOSFET in the presence of Interfacial Traps

In this paper, we propose a new analytical volume inversion charge density model for SGCG DG MOSFET. The proposed architecture diminishes the short channel effects (SCEs) as well as interfacial trap effects. The proposed structure has a gate length of 20 nm and width 10 nm. The channel is divided into three regions, the channel density of region I is kept low i.e., 10
²¹
m
^-3
and for regions II and III, the channel densities are high i.e., 10
²³
m
^-3
. The interfacial traps which are acceptor type present in the damaged region III having concentration 1.5 × 10
¹⁶
m
^-2
. The volume inversion charge density model is derived in the subthreshold regime using subthreshold current model. The findings of previously published experiments are used to validate the data from the drain current modeling and a good agreement is noticed. It has been demonstrated how different device parameters, such as channel thickness and high-k material thickness, affect the device's drain current and volume inversion charge as a function of gate voltage.